View MX803A_1361299.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

data bulletin MX803A ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 audio signaling processor preliminary information features applications full duplex audio signaling processor single tone selective call systems tone decoder with programmable notone timer. two individual tone encoders and a programmable tx period timer. low power cmos device on-chip programmable amplifier. c-bus compatible signaling systems supported selcall (ccir, eea, zvei i / ii /iii) 2-tone selcall dtmf encode inband tone signaling capability for lmr and other radio systems. (rx) audio in signal input bias digital noise filter 1 digital noise filter 2 quality meter gate time generator frequency counter programmable (tx period) timer programmable notone timer c-bus interface and control logic command data reply data chip select interrupt serial clock logic input tone 1 out sum in switched sum out sum out cal/cues out tone 2 out switch out tone 1 generator 5-/2-tone dtmf 1 summing amplifier clock generator xtal/ clock xtal audio switch in tone 2 generator cues/dtmf 2 low pass filter low pass filter v ss v bias v bias v dd rx filter switch _ + summing switch cal/cues switch cues cal audio switch the MX803A is an audio signaling processor that provides inband tone signaling capabilities for lmr and other radio systems. a low-power cmos device, the MX803A is a member of the dbs800 (digitally integrated baseband sub- system) ic family (see section 4.2). supported signaling systems include selcall (ccir, eea, zvei i, ii, and iii) 2-tone selcall and dtmf encode. the use of a non-predictive decoder and a versatile encoder, allows the MX803A to operate in any standard or non-standard tone system. the MX803A is a full-duplex device for use with single tone or selective call systems. the MX803A consists of a tone decoder with a programmable notone timer, two individual tone encoders and a programmable tx period timer, and an on-chip summing amplifier. under the control of a m c, the MX803A will simultaneously encode and transmit 1 or 2 audio tones in the 208-3000hz range, as well as detect, decode, and indicate the frequency of any non-predicted input tone in the frequency range of 313 to 6000hz. the MX803A is available in 24-pin cdip (MX803Aj), 24-pin plcc (MX803Alh), and 24-pin soic (MX803Adw) packages.
audio signaling processor 2 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 contents section page 1. block diagram ............................................................................................................... ................... 3 2. signal list ................................................................................................................. ........................ 4 3. external components ......................................................................................................... ............. 6 4. general description ......................................................................................................... ................ 7 4.1 description................................................................................................................ .......................... 7 4.2 dbs800 systems ............................................................................................................. ......................... 7 4.3 c-bus control .............................................................................................................. ............................ 8 5. application ................................................................................................................. ...................... 8 5.1 MX803A internal registers .................................................................................................. ..................... 8 5.2 address/commands........................................................................................................... ....................... 9 5.3 powersave .................................................................................................................. ............................. 18 5.4 interrupt request irq .............................................................................................................................. 1 9 5.5 operational recommendations................................................................................................ ................ 19 5.6 general reset .............................................................................................................. ............................ 20 6. timing information.......................................................................................................... ................ 20 7. performance specification................................................................................................... .......... 22 7.1 electrical performance ..................................................................................................... ........................ 22 7.2 packaging .................................................................................................................. .............................. 25 mx?com, inc. reserves the right to change specifications at any time and without notice.
audio signaling processor 3 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 1. block diagram (rx) audio in signal input bias digital noise filter 1 digital noise filter 2 quality meter gate time generator frequency counter programmable (tx period) timer programmable notone timer c-bus interface and control logic command data reply data chip select interrupt serial clock logic input tone 1 out sum in switched sum out sum out cal/cues out tone 2 out switch out tone 1 generator 5-/2-tone dtmf 1 summing amplifier clock generator xtal/ clock xtal audio switch in tone 2 generator cues/dtmf 2 low pass filter low pass filter v ss v bias v bias v dd rx filter switch _ + summing switch cal/cues switch cues cal audio switch figure 1: block diagram
audio signaling processor 4 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 2. signal list pin no. name type description 1 xtal output output of the on-chip clock oscillator. external components are required at this output when a xtal is used. see figure 2. 2 xtal/clock input input to the on-chip clock oscillator inverter. a xtal or externally derived clock should be connected here. see figure 2. 3 reply data output c-bus serial data output to the m c. the transmission of reply data bytes is synchronized to the serial clock under the control of the chip select input. this 3-state output is held at high impedance when not sending data to the m c. see figure 8 and figure 9. 4 cs input c-bus data loading control function. this input is provided by the m c. data transfer sequences are initiated, completed or aborted by the chip select signal. see figure 8 and figure 9. 5 command data input c-bus serial data input from the m c. data is loaded to this device in 8-bit bytes, msb (b7) first and lsb (b0) last, synchronized to the serial clock. see figure 8 and figure 9. 6 logic input input this real-time input is available as a general purpose logic input port which can be read from the status register. see table 3. g/purpose timer period expired notone timer period expired rx tone measurement complete these interrupts are inactive during relevant powersave conditions and can be disabled by bits 5 and 6 in the control register. 7 irq output output of this pin indicates an interrupt condition to the m c by going to a logic 0. this is a wire-or-able output, allowing the connection of up to 8 peripherals to 1 interrupt port on the m c. this pin has a low impedance pulldown to logic 0 when active and a high impedance when inactive. the system irq line requires one pullup resistor to v dd . the conditions that cause interrupts are indicated in the status register and are shown below: 10 audio switch in input input to the stand-alone on-chip audio switch. this function is enabled/disabled by bit 7 of the control register 11 audio switch out output output of the stand-alone on-chip audio switch.. 12 v ss power negative supply (gnd). 13 rx audio in input received audio tone signaling input. this input must be ac coupled and connected, using external components, to the signal input bias pin. see figure 2. 14 signal input bias input external components are required between this input and the rx audio in pin. see figure 2. 15 v bias output internal circuitry bias signal, held at v dd /2. this pin should be decoupled to v ss by capacitor c2. see figure 2.. 16 tone 1 out output tone 1 generator (2-/5-tone selcall or dtmf 1) output. external gain and coupling components are required at this output when operating in a complete dbs 800 audio installation. the frequency of this output is determined by writing to the tx tone generator 1 register (table 5). see figure 2. 17 tone 2 out output tone 2 generator (2-/5-tone selcall, cues or dtmf 2) output. external gain and coupling components are required at this output when operating in a complete dbs 800 audio installation. the frequency of this output is determined by writing to the tx tone generator 2 register (table 5). see figure 2.
audio signaling processor 5 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 pin no. name type description 18 cal/cues out output an auxiliary, selectable tone frequency output, providing a square wave calibration signal from the tone 2 generator or a sine wave cues (beep) signal from the summing amplifier. the output mode (cal or cues) is selected by bit 14 in the tx tone generator 2 register (table 5). when tone generator 2 is set to notone, the cal input is pulled to v bias ; during a powersave of tone generator 2 it is held at v ss . 19 sum in input input to the on-chip summing amplifier. this amplifier is available for combining tone 1 and tone 2 outputs (dtmf). gain and coupling components should be used at this input to provide the required system gains. see figure 2 and figure 3 20 sum out output output of the on-chip summing amplifier. combined tones (1 and 2) are available at this output. see figure 2 and figure 3. 21 switched sum out output this is the combined tone output available for transmitter modulation. the switch allows control of the MX803A output. control of this switch is by bit 4 of the control register. see figure 2 and figure 3. 23 serial clock input c-bus serial clock input. this clock, produced by the m c, is used for transfer timing of commands and data to and from the MX803A. see figure 8 and figure 9. 24 v dd power positive supply. a single +5 volt power supply is required. levels and voltages within this audio signaling processor are dependent upon this supply.. 8, 9, 22 n/c no internal connection. these pins may be connected to v ss to improve screening and reduce noise levels around the MX803A.
audio signaling processor 6 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 3. external components MX803A inset see inset below 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 xtal xtal/clock reply data cs command data logic input irq audio switch in audio switch out v r r x c c c c r r r r c c v bias v bias ss 7 1 1 4 1 2 3 2 4 r 6 3 5 5 6 v dd serial clock switched sum out sum out sum in cal/cues out tone 2 out tone 1 out signal bias rx audio in xtal xtal/clock 1 2 MX803A tone level and gain components r1 1.0m w 10% c1 0.1 m f 20% r2 2.0m w 10% c2 1.0 m f 20% r3 note 2, 3 100k w 10% c3 note 4 33.0pf 20% r4 note 2, 3 82.0k w 10% c4 note 4 33.0pf 20% r5 note 2, 3 122k w 10% c5 note 3 22.0pf 20% r6 note 2 100k w 10% c6 1.0 m f 20% r7 note 2, 5 100k w 10% x1 note 1, 4 4.00mh z figure 2: recommended external components notes: 1. xtal/clock components described are recommended in accordance with mx-com's application note on standard and dbs 800 crystal oscillator circuits (april 1990). for best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of v dd , peak to peak. tuning fork crystals generally cannot meet this requirement. to obtain crystal oscillator design assistance, consult your crystal manufacturer. 2. system components whose values are calculated to allow the MX803A to operate with other dbs 800 microcircuits. figure 3 shows these components used in the system signal paths. 3. r3, r4, r5 and c5 are tone mixing components calculated to provide a 3db tone differential (twist) for use in a dtmf configuration. single tone output levels are set independently. 4. when x1 > 5.00mhz, c3 = c4 = 18pf 5. r7 provides modulation level and matching outputs for the MX803A.
audio signaling processor 7 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 + _ 17 16 bias 19 11 18 10 21 20 tone 2 out tone 1 out sum in dbs 800 transmit audio bus from mx806a main process out audio switch in audio switch out cal/cues out switched sum out sum out summing amplifier to mx806a calibration in cal cues to mx806a sum in MX803A figure 3: example of signal switching in a dbs800 microcircuit 4. general description 4.1 description the MX803A is an audio signaling processor that provides inband tone signaling capabilities for lmr and other radio systems. a low-power cmos device, the MX803A is a member of the dbs800 (digitally integrated baseband sub- system) ic family (see section 4.2). supported signaling systems include selcall (ccir, eea, zvei i, ii, and iii) 2-tone selcall and dtmf encode. the use of a non-predictive decoder and a versatile encoder, allows the MX803A to operate in any standard or non-standard tone system. the MX803A is a full-duplex device for use with single tone or selective call systems. the MX803A consists of a tone decoder with a programmable notone timer, two individual tone encoders and a programmable tx period timer, and an on-chip summing amplifier. under the control of a m c, the MX803A will simultaneously encode and transmit 1 or 2 audio tones in the 208-3000hz range, as well as detect, decode, and indicate the frequency of any non-predicted input tone in the frequency range of 313 to 6000hz. a general purpose logic input, interfacing directly with the status register, is provided. this may be used as an auxiliary method of routing digital information to the m c via c-bus. output frequencies are produced from data loaded to the MX803A. a programmable, general purpose, on-chip timer sets the tone transmit periods. a dual-tone multi-frequency (dtmf) output is obtained by combining the 2 independent output frequencies in the integral summing amplifier. this process can also be used for level correction. tones produced by the MX803A can be used in the system as modulation calibration inputs and as cue audio indications to the operator. received tones are measured and their frequency indicated to the m c in the form of a received data word. a poor quality or incoherent tone will indicate notone. 4.2 dbs800 systems the digitally-integrated baseband subsystem (dbs800) is a family of low power ics which provide a comprehensive range of audio processing and signaling functions for use within lmr and other radio systems. each dbs800 ic may be used as part of a complete audio system, or each ic may operate as a stand alone. the system and ics are partitioned in such a way that radio designers can easily select the device or devices appropriate to their needs. the dbs800 family consists of the following ics: 4.2.1 mx802 dvsr codec this is a full-duplex cvsd speech encoder/decoder with the ability to store and retrieve data within attached dram (dynamic random access memory) using an on-chip dram controller. the mx802 also provides on-chip input and output audio filtering. 4.2.2 MX803A audio signaling processor this provides an inband tone signaling ability to lmr and other radio systems.
audio signaling processor 8 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 4.2.3 mx805a sub-audio signaling processor this provides a sub-audio and digital signaling (nrz) ability to lmr and other radio systems. 4.2.4 mx806a audio processor this is a half duplex audio processor providing all dbs800 system audio signal conditioning and filtering capabilities for the system transmit and receive paths. 4.2.5 mx809 msk modem this is an intelligent, half-duplex 1200bps msk/ffsk modem with software programmable byte-synchronization system and checksum generation and checking. 4.2.6 mx812 vsr codec this is a half-duplex cvsd speech encoder/decoder with the ability to store and retrieve data within attached dram (dynamic random access memory) using an on-chip dram controller 4.3 c-bus control c-bus is the controlling hardware and software interface for all members of the dbs800 family. it enables the serial, bi- directional transfer of commands and data throughout the system, allowing total flexibility of operational control and data handling. system upgrades can be achieved by a simple software or firmware change. the c-bus physically consist of 5 lines. these lines are serial clock, command data, reply data, chip select ( cs ), and interrupt request ( irq ). a description of each may be found in section 2. 5. application control of the MX803A audio signaling processor's operation is by communication between the m c and the MX803A internal registers on the c-bus using address/commands (a/cs) and appended instructions or data. see figure 8. the use and content of these instructions is detailed in the following sections. for additional application information contact mx com, inc. 5.1 MX803A internal registers control register 30 h write only, control and configuration of the MX803A. status register 31 h read only, reporting of device functions. rx tone frequency register 32 h read only, indicates frequency of the last received input. rx notone timer 33 h write only, setting of the rx notone period. tx tone generator 1 register 34 h write only, setting the required output frequency from tx tone generator 1. tx tone generator 2 register 35 h write only, setting the required output frequency from tx tone generator 2. general purpose timer register 36 h write only, setting of a general purpose sequential time period.
audio signaling processor 9 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 5.2 address/commands the first byte of a loaded data sequence is always recognized by the c-bus as an address/command (a/c) byte. instruction and data transactions to and from this device consist of an a/c byte followed by further instruction/data or a status/data reply. instructions and data are loaded and transferred via c-bus in accordance with the timing information given in figure 8 and figure 9. table 1 shows the list of a/c bytes relevant to the MX803A. command assignment address/command (a/c) byte data bytes hex binary msb lsb general reset 01 00000001 write to control register 30 00110000 + 1 byte instruction to control register read status register 31 00110001 + 1 byte reply from status register read rx tone frequency 32 00110010 + 2 bytes reply from rx tone register write to notone timer 33 00110011 + 1 byte instruction to notone register write to tx tone gen. 1 34 00110100 + 2 bytes instruction to tx tone gen. 1 write to tx tone gen. 2 35 00110101 + 2 bytes instruction to tx tone gen. 2 write to g/purpose timer 36 00110110 + 1 byte instruction to g/purpose timer table 1: c-bus address/commands 0 1000 208hz to 3000hz 625hz to 3000hz 313hz to 1500hz 1250hz to 6000hz 2000 3000 4000 5000 6000 0 1000 2000 3000 4000 5000 6000 frequency (hz) (tx) tone generators 1 and 2 (rx) mid band (rx) high band (rx) extended band figure 4: MX803A frequencies
audio signaling processor 10 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 5.2.1 write to control register a/c 30 h , followed by 1 byte of command data audio switch: enables or disables the stand-alone on-chip audio switch. general purpose timer: this should be set up before interrupts are enabled since a general reset command will set the timer period to 00 h - 0ms (permanent interrupt). interrupt enable instructions: status bits 0, 1 and 2 are produced regardless of the state of these settings. band selection: bits 2 and 3 set the required frequency range. see figure 4. summing switch: used to enable or disable the switch that controls the MX803A output. interrupt designation: decoder interrupts notone timer and rx tone measurement transmitter interrupt g/purpose timer interrupt setting control bits msb transmitted first bit 7 audio switch 1 enable 0 disable bit 6 g/purpose timer interrupt 1 enable 0 disable bit 5 decoder interrupts 1 enable 0 disable bit 4 summing switch 1 enable 0 disable bit 3 bit 2 band selection 0 0 high band 0 1 mid band 1 0 extended band 1 1 do not use this setting bit 1 set to 00 bit 0 set to 00 table 2: control register
audio signaling processor 11 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 5.2.2 read status register a/c 31 h , followed by 1 byte of reply data interrupt requests (irq): interrupts on this device are available to draw the attention of the m c to a change in the condition of the bit in the status register. however, bits are set in the status register irrespective of the setting of interr upt enable bits (table 2) and these changes may be recognized by polling the register. general purpose timer period: set to a logic 1 when the timer period has expired. cleared to a logic 0 by: 1. reading the status register 2. new g/purpose timer information 3. general reset command notone timer period: set to a logic 1 when the timer period has expired. cleared to a logic 0 by: 1. reading the status register 2. new notone timer information 3. general reset command rx tone measurement: set to a logic 1 when the rx tone measurement is complete. cleared to a logic 0 by: 1. reading the status register 2. general reset command setting status bits msb received first bit 7 set to 00 bit 6 set to 00 bit 5 set to 00 bit 4 set to 00 bit 3 logic input status 11 00 bit 2 g/purpose timer period 1expired (interrupt generated) bit 1 notone timer period 1expired (interrupt generated) bit 0 rx tone measurement 1 complete (interrupt generated) table 3: status register
audio signaling processor 12 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 5.2.3 tx tone generator registers 1 and 2 each tx tone generator is controlled individually by writing a two-byte command to the relevant tx tone generator register. the format of this command word, which is different for each tone generator, is shown below with the calculations required for tone frequency (f tone ) generation described in the following text. 5.2.3.1 write to tx tone generator 1 register a/c 34 h , followed by 2 bytes of command data msb (loaded first) bit numbers lsb (loaded last) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 notone/enable these 13 bits (0 to 12) are used to produce a binary number, designated a. a is used in the formulas below to set the tx tone 1 frequency (f tone 1). table 4: tx tone generator 1 5.2.3.1.1 setting tx tone generator 1 the binary number produced by bits 0 to 12 (msb) is designated a. if a = all logic 0 tx tone generator 1 is powersaved. bit 13 at logic 1 = tone 1 output at v bias (notone) 0 = tone 1 output enabled bits14 and15(msb) must be logic 0 5.2.3.2 write to tx tone generator 2 register a/c 35 h , followed by 2 bytes of command data msb (loaded first) bit numbers lsb (loaded last 15 14 13 1211109876543210 0 cal/cues notone/enable these 13 bits (0 to 12) are used to produce a binary number, designated b. b is used in the formulas below to set the tx tone 2 frequency (f tone 2). table 5: tx tone generator 2 write to tx tone generator 2 register notes: programming tone generator 2 to notone will place the cal/cues output at v bias via a 40k w internal resistor. programming tone generator 2 to powersave will place the cal/cues output at v ss . if both tone generators are powersaved, the input amplifier is also powersaved 5.2.3.2.1 setting tx tone generator 2 the binary number produced by bits 0 to 12 (msb) is designated b. if b = all logic 0 then tx tone generator 2 is powersaved. bit 13 at logic 1 = tone 1 output at v bias (notone) 0 = tone 1 output enabled bit 14 at logic 1 = squarewave cal output 0 = sinewave cues output bit 15 (msb) must be a logic 0.
audio signaling processor 13 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 5.2.3.3 calculations as seen in table 4 and table 5, a binary number (a or b - bits 0 to 12) is loaded to the respective tx tone generator. the formulas described below are used to produce the required output frequency. required tx tone output frequency = f tone 1 or 2 xtal/clock frequency = f xtal input data word (bits 0 to 12) = a or b f = f 4 ' a' or 'b' hz or input ' a' or 'b' = f 4 f hz tone xtal xtal tone 5.2.3.4 tx tone frequencies with reference to table 4 and table 5, while input data words a or b can be programmed for frequencies outside the stated limits of 208hz and 3000hz, any output frequencies obtained may not be within specified parameters. see section 7. 5.2.4 read rx tone frequency register a/c 32 h , followed by 2 bytes of reply data 5.2.4.1 measurement of rx signal frequency s in the input audio signal, s in , is measured in the frequency counter over a specified measurement period (9.125ms or 18.250ms). the measuring function counts the number of complete input cycles occurring within the count period and then the number of measuring clock cycles necessary to make up the period. when the count period of a successful decode is complete, the rx tone measurement bit in the status register and the interrupt bit are set. the rx tone frequency register will now indicate the signal frequency s in in the form of 2 bytes (1 and 0) as illustrated in figure 6. note: the following measurements are based on a clock frequency of 4.032 mhz. see section 5.2.4.4 for a scaling formula for other crystal values). complete input cycle complete input cycle complete input cycle complete input cycle complete input cycle measuring clock cycles measurement period n r filtered audio input signal 2 x s input figure 5: measurement of an rx frequency 5.2.4.2 the integer (n) - byte 1 this is a binary number representing twice the number of complete input audio cycle periods. it is counted during the specified measurement period (t), when (t) is: hi g h band decode = 9.125ms mid band decode = 18.250ms extended band decode = 9.125ms note : see section 5.2.4.4 for calculation of measurement period (t) using a xtal other than 4.032mhz.
audio signaling processor 14 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 5.2.4.3 the remainder (r) - byte 0 this is a binary number representing the remainder part, r, of twice the input signal frequency. r = the number of specified measuring-clock cycles required to complete the specified measurement period (see 5.2.4.2). the clock cycle frequency (f) is: hi g h band decode = 56.00khz mid band decode = 28.00khz extended band decode = 56.00khz note : see section 5.2.4.4 for calculation of clock cycle frequency (f) using a xtal other than 4.032mhz. ? ? ? ? figure 6: format of the rx tone frequency register 5.2.4.4 f xtal scaling factors the following formulas allow the calculation of the integer n (see section 5.2.4.2) and the remainder r (see section 0) using any xtal value. t scaled = t x 4.032 f f scaled = f x f 4.032 xtal xtal ? ? ? ? ? ? ? ? 5.2.5 frequency measurement the following formulas show the derivation of the rx frequency s in from the measured data bytes (n and r) note: the following measurements are based on a clock frequency of 4.032 mhz. see section 5.2.4.4 for a scaling formula for other xtal values. 5.2.5.1 high band measurement s in - high band n and r - high band in the measurement period of 9.125ms, there are n cycles at 2s in and r clock cycles at 56.000khz. the measurement period = 9.125ms. clock frequency = 56.000khz the measured frequency = 2s in hz in the measurement period there are: () n s in 2 + r 56000 = 9.125ms from which s = 28000 x n 511 - r in 2s in x 9.125 x 10 cycles -3 n high is the lower integer value of the decimal number: n = int (9.125 x 10 x 2s ) -3 in r high is the lower integer value of the decimal number: r = int (9.125 x 10 - 3 - n 2s ) x 56000 in
audio signaling processor 15 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 5.2.5.2 mid band measurement s in - mid band n and r - high band in the measurement period of 18.250ms, there are n cycles at 2s in and r clock cycles at 28.000khz. the measurement period = 18.250ms. clock frequency = 28.000khz the measured frequency = 2s in hz in the measurement period there are: () n s in 2 + r 28000 = 18.250ms from which s = 14000 x n 511 - r in 2s in x 18.250 x 10 cycles -3 n mid is the lower integer value of the decimal number: n = int (18.250 x 10 x 2s ) -3 in r mid is the lower integer value of the decimal number: r = int (18.250 x 10 - n 2s ) x 28000 -3 in 5.2.5.3 extended band measurement s in - extended band n and r - high band in the measurement period of 9.125ms, there are n cycles at 2s in and r clock cycles at 56.000khz. the measurement period = 9.125ms. clock frequency = 56.000khz the measured frequency = 2s in hz in the measurement period there are: () n s in 2 + r 56000 = 9.125ms from which s = 28000 x n 511 - r in 2s in x 9.125 x 10 cycles -3 n extended is the lower integer value of the decimal number: n = int (9.125 x 10 x 2s ) -3 in r extended is the lower integer value of the decimal number: r = int (9.125 x 10 - 3 - n 2s ) x 56000 in 5.2.6 write to rx notone timer register a/c 33 h , followed by 1 byte of command data 5.2.6.1 operation of the rx notone timer a notone period is that period when no signal or a consistently bad quality signal is received. the notone timer is employed to indicate to the m c that a notone situation has existed for a predetermined period. the notone timer period is primed by writing to the notone timer register (33 h ) using the instructions and information (1 data byte) given in table 6. this timer register can be written-to and set in any mode of the MX803A except notone timer powersave. priming the timer sets the timing period; this period will not be allowed to start until at least one frequency (tone) measurement has been successfully completed. the notone timer is a one-shot timer that is reset only by successful tone measurements. if the quality of the received signal drops to an unusable level the notone timer will start its run-down. on completion of this timer period, the notone timer period expired bit in the status register and an interrupt are set. upon detection of the interrupt, the status register should be read by the m c to ascertain the source of the interrupt.
audio signaling processor 16 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 the notone timer period expired bit is cleared: 1. by a read of the status register. 2. new notone timer information 3. general reset command the timer is set to 00 h by a general reset command. setting function / period msb 7 6 5 4 transmitted bit 7 first 0 0 0 0 these 4 bits must be 0 period (ms) 3 2 1 0 high band % mid band % 0000 0 0 0001 20 1 40 1 0010 40 1 80 1 0011 60 1 120 1 0100 80 1 160 1 0 1 0 1 100 1 200 1 0 1 1 0 120 1 240 1 0 1 1 1 140 1 280 1 1 0 0 0 160 1 320 1 1 0 0 1 280 1 360 1 1 0 1 0 200 1 400 1 1 0 1 1 220 1 440 1 1 1 0 0 240 1 480 1 1 1 0 1 260 1 520 1 1 1 1 0 280 1 560 1 1 1 1 1 300 1 600 1 table 6: rx notone timer settings 5.2.6.2 notone timer circuitry the following situations may be encountered by the notone timer circuitry 5.2.6.2.1 no signal the notone timer can only start its run down on completion of a valid frequency measurement. 5.2.6.2.2 no signal after a valid tone measurement the timer will start to run down when the last rx tone measurement complete bit is set. at the end of the primed period the notone timer period expired bit in the status register and the interrupt will be set. 5.2.6.2.3 signal fades after a valid tone measurement the timer will start to run down when the signal becomes unreadable to the device. at the end of the primed period the notone timer period expired bit in the status register and the interrupt will be set. 5.2.6.2.4 signal appears after the timer has started if the frequency measurement is more than 75% complete when the timer period expires, neither the notone bit nor the interrupt will be set unless that frequency measurement is subsequently aborted.
audio signaling processor 17 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 signal input notone timer s input s input s input notone timer notone timer valid tone "rx measure complete" set "rx measure complete" set "rx measure complete" set "rx measure complete" set "rx measure complete" set "rx measure complete" set "rx measure complete" set timing period "primed" timing period "primed" timing period "not reset" timing period "reset" timing period "primed" signal fades "rx notone timer expired" and not set "rx notone timer expired" and set signal lost and recovered figure 7: notone timing 5.2.7 write to general purpose timer register a/c 36 h , followed by 1 byte of command data 5.2.7.1 operation of the general purpose timer this timer, which is not dedicated to any specific function within the MX803A, can be used within the dbs 800 system to indicate time-elapsed periods of between 10-150ms in the high band or 20-300ms in the mid band to the m c. setting of the timer is by loading a single byte data word via the c-bus (see table 7) to the MX803A through the command data line. the timer will be reset and the run-down started on completion of timer data word loading. when the programmed time period has expired, the general purpose timer expired bit (bit 2) in the status register and the interrupt are set. the general purpose timer expired bit is cleared: 1. by a read of the status register 2. new g/p timer information 3. general reset command.
audio signaling processor 18 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 when the programmed time period has expired, this timer will reset, restart itself and continue sequencing until: 1. new g/p timer information is written 2. a general reset command is received. the general purpose timer expired bit and the interrupt will remain set until cleared. the timer is set to 00 h (0ms) by a general reset command. setting function / period msb 7 6 5 4 transmitted bit 7 first 0 0 0 0 these 4 bits must be 0 reset timer and start timing period (ms) 3 2 1 0 high band % mid band % 0000 0 0 0001 10 1 20 1 0010 20 1 40 1 0011 30 1 60 1 0100 40 1 80 1 0101 50 1 100 1 0110 60 1 120 1 0111 70 1 140 1 1000 80 1 160 1 1001 90 1 180 1 1 0 1 0 100 1 200 1 1 0 1 1 110 1 220 1 1 1 0 0 120 1 240 1 1 1 0 1 130 1 260 1 1 1 1 0 140 1 280 1 1 1 1 1 150 1 300 1 table 7: general purpose timer settings 5.3 powersave various sections of the MX803A can be placed independently into a power-economical condition. table 8 gives a summary of these states available to the MX803A. powersaved section instruction source table tone encoder 1 tx tone gen. 1 reg. (34 h ) all bits = 0 table 4 tone encoder 2 tx tone gen. 2 reg. (35 h ) all bits = 0 table 5 input amplifier this action is automatic when both tone encoders are in the powersave condition table 8: MX803A powersave functions 5.3.1 powersave conditions xtal/clock and c-bus : this circuitry is always active, on all dbs 800 ics, under any depowered/powersaved conditions
audio signaling processor 19 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 5.4 interrupt request irq an interrupt (irq), when enabled, is provided by the MX803A to indicate the following conditions to the m c. notone timer period expired g/purpose timer period expired rx tone measurement complete enabled by control resister bit 5 by control resister bit 6 by control resister bit 5 set when the preset notone flag is set when the general purpose timer has timed out. when an rx frequency measurement has been successfully completed identified by status register bit 1 by status register bit 2 by status register bit 0 cleared by reading the status register by reading the status register by reading the status register table 9: interrupt request on recognition of the read status command byte, the interrupt output is cleared, the status bits are transferred to the m c via the c-bus reply data line and the internal status bits are cleared. 5.5 operational recommendations following initial system power-up, a general reset command should be sent. 5.5.1 receive sequence 1. send control command for rx: select midband/highband and digital filter length. 2. disable transmitters if desired by writing to tone frequency registers. 3. prime the notone timer by sending the required period byte. 4. enable/disable interrupts as desired. 5. when a valid tone has been detected by a successfully completed measurement the status register is set to tone measurement complete and an interrupt is set to the m c. 6. the m c examines the status register. if tone measurement is complete, it reads in the rx tone frequency in the form n + r (figure 6). 7. rx tone measurement complete interrupts are periodically sent to the m c unless notone is detected, in which case a notone interrupt is sent. 5.5.2 transmit sequence 1. set tone frequency generators to notone during the transmitter initialization period. 2. send control command for tx: select sum/switched sum out and audio switch states. 3. send general purpose (gp) timer information for the notone transmitter initialization period. this will initiate the timer. 4. enable/disable interrupts as desired. 5. m c waits for gp timer expired, reads the status register to check interrupts due to timer, and resets the status bit. if required, the m c sends the next timer period followed by the next tone(s) frequency information. a new timer period sent will reset the timer, otherwise the timer is self-resetting. 6. the m c monitors the interrupts and repeats steps 5 and 6 as required. 7. after last loaded tone, m c turns off tone generator(s).
audio signaling processor 20 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 5.6 general reset upon power-up the bits in the MX803A registers will be random (either 0 or 1). a general reset command (01 h ) will be required to reset all microcircuits on the c-bus. it has the following effect on the MX803A: control register set as 00 h status register (bits 0, 1, 2) set as 00 h notone timer set as 00 h tone gen. 1 reg. (2 bytes) set as 0000 h tone gen. 2 reg. (2 bytes) set as 0000 h gen. purpose reg. set as 00 h table 10: general reset effect on MX803A this sets the MX803A to encoder high band (625hz to 3000hz) with interrupts disabled and both timers set to 00 h . both timers should be set up before interrupts are enabled to prevent initial, undesired interrupts. 6. timing information figure 8 shows timing parameters for two-way communication between the m c and the MX803A on the c-bus. chip select serial clock command data reply data address/command byte first data byte last data byte first reply data byte last reply data byte logic level is not important msb lsb 76543210 76543210 76543210 msb lsb 76543210 76543210 t csoff t ck t nxt t hiz t cse t nxt t nxt figure 8: c-bus timing
audio signaling processor 21 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 parameter min typ max unit t cse chip select low to first serial clock rising edge 2.0 m s t csh last serial clock rising edge to chip select high 4.0 m s t csoff chip select high 2.0 m s t nxt command data inter-byte time 4.0 m s t ck serial clock period 2.0 m s t ch decoder or encoder clock high 500 ns t cl decoder or encoder clock low 500 ns t cds command data set-up time 250 ns t cdh command data hold time 0 ns t rds reply data set-up time 250 ns t rdh reply data hold time 50.0 ns t hiz chip select high to reply data high - z 2.0 m s table 11: timing information timing information notes 1. command data is transmitted to the peripheral msb (bit 7) first, lsb (bit 0) last. reply data is read from the MX803A msb (bit 7) first, lsb (bit 0) last. 2. data is clocked into the MX803A and into the m c on the rising serial clock edge. 3. loaded data instructions are acted upon at the end of each individual, loaded byte. 4. to allow for differing m c serial interface formats, the MX803A will work with either polarity serial clock pulses. t t t t t t t ch ck cdh rdh rds cds cl 70% vdd 30% vdd command data (from c) serial clock (from c) reply data (to c) figure 9: timing relationship for c-bus information transfer
audio signaling processor 22 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 7. performance specification 7.1 electrical performance absolute maximum ratings exceeding these maximum ratings can result in damage to the device. operation of the device outside of the operating limits is not suggested. general min. max. units supply voltage (v dd - v ss ) -0.3 7.0 v voltage on any pin to v ss -0.3 v dd + 0.3 v current v dd -30 30 ma v ss -30 30 ma any other pins -20 20 ma dw / j / lh packages operating temperature -40 85 c storage temperature -55 125 c total allowable power dissipation at t amb = 25 c 800 mw derating above 25 c 10 mw/ c above 25 c operating limits all devices were measured under the following conditions unless otherwise noted. notes min. max. units supply (v dd -v ss )4.55.5v temperature -40 85 c xtal/clock frequency 4.0 mhz
audio signaling processor 23 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 operating characteristics for the following conditions unless otherwise specified: v dd = 5.0 @ t amb = 25 c xtal = 4mhz (refer to section 5.2.4.4 for xtal scaling factor) audio level 0db ref. = 308mv rms @ 1khz (60% deviation, fm) noise bandwidth = 5.0khz band-limited gaussian notes min. typ. max. units static values supply voltage 4.5 5.0 5.5 v supply current decoder + both timers 2.0 ma decoder, both timers + one tx only 4.0 ma all functions enabled 5.0 ma analog impedance rx audio input 20.0 m w summing amp input 20.0 m w switch 1.0 k w tones 1 and 2 outputs 10.0 k w cal/cues output 5.0 k w summing outputs 10.0 k w dynamic values digital interface input logic 1 1 3.5 v input logic 0 1 1.5 v output logic 1 (i oh = -120 m a) 2 4.6 v output logic 0 (i ol = 360 m a) 3 0.4 v i out tristate (logic 1 or 0) 3 4.0 m a input capacitance 1 7.5 pf i ox (v out = 5v) 4 4.0 m a overall performances rx - decoding high band sensitivity -20.0 db tone response time good signal 5,10 30.0 ms tone-to-noise ratio = 0db 5,6,10 40.0 ms frequency band 625 3000 hz measurement resolution 0.2 % measurement accuracy 9 0.5 %
audio signaling processor 24 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 notes min. typ. max. units mid-band sensitivity -20.0 db tone response time good signal 7,10 60.0 ms tone-to-noise ratio = 0db 6,7,10 80.0 ms frequency band 313 1500 hz measurement resolution 0.2 % measurement accuracy 9 0.5 % extended band sensitivity -20.0 db tone response time good signal 5,10 20.0 ms frequency band 1250 6000 hz measurement resolution 0.2 % measurement accuracy 9 0.5 % tx - encoders 1 and 2 tone frequency 208 3000 hz period (1/f tone ) error 1.0 m s tone amplitude -1.5 1.5 db total harmonic distortion 5.0 % rise time to 90% 3/f tone ms fall time to 10% 8 5.0 ms frequency change time 3/f tone ms timers general purpose timing period range high-band 10.0 150 ms mid-band 20.0 300 ms rx notone timing period range hi-band 20.0 300 ms mid-band 40.0 600 ms xtal/clock frequency (f xtal ) 4.0 6.0 mhz
audio signaling processor 25 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 operating characteristics notes: 1. device control pins: serial clock, command data, and cs . 2. reply data output. 3. reply data and irq outputs. 4. leakage current into the off irq output. 5. measurement period = 9.198ms. 6. decode probability = 0.993. 7. measurement period = 18.396ms. 8. when set to powersave. 9. for a good input signal. 10. inversely proportional to xtal frequency, i.e. spec. x 4mhz f xtal . so, for a 6mhz clock a 30ms tone response time becomes 20ms. 7.2 packaging 0.597 (15.16) package tolerances a b c e h typ. max. min. dim. j p x w t y k l 0.105 (2.67) 0.093 (2.36) 0.419 (10.64) 45 7 0 10 0.050 (1.27) 0.046 (1.17) 0.613 (15.57) 0.299 (7.59) 0.050 (1.27) 0.016 (0.41) 0.390 (9.90) 0.020 (0.51) 0.003 (0.08) 0.009 (0.23) 0.0125 (0.32) 0.013 (0.33) 0.020 (0.51) 0.036 (0.91) 0.286 (7.26) z note : all dimensions in inches (mm.) angles are in degrees 5 5 pin 1 a b alternative pin location marking x p j y c h k e l t w z figure 10: 24-pin soic mechanical outline: order as part no. MX803Adw
audio signaling processor 26 MX803A preliminary information ? 1996 mx com, inc. tele: 800 638 5577 910 744 5050 fax: 910 744 5054 doc. # 20480122.003 package tolerances note : all dimensions in inches (mm.) angles are in degrees a b c d e h p f g typ. max. min. dim. k j w t y 0.435 (11.05) 0.435 (11.05) 0.051 (1.30) 0.009 (0.22) 6 30 0.409 (10.40) 0.409 (10.40) 0.146 (3.70) 0.417 (10.60) 0.417 (10.60) 0.049 (1.24) 0.006 (0.152) 0.250 (6.35) 0.250 (6.35) 0.023 (0.58) 0.047 (1.19) 0.022 (0.55) 0.018 (0.45) 0.380 (9.61) 0.380 (9.61) 0.128 (3.25) 0.048 (1.22) 45 f g p a d b e pin 1 w c j k y w h t figure 11: 24-pin plcc mechanical outline: order as part no. MX803Alh note : all dimensions in inches (mm.) angles are in degrees package tolerances a b c e e1 f h typ. max. min. dim. j j1 p t k1 k l 0.230 (5.84) 0.583 (14.79) 0.670 (17.00) 0.200 (5.08) 1.260 (32.00) 0.165 (4.19) 0.10 (2.54) 0.115 (2.92) 0.600 (15.23) 0.594 (15.09) 0.615 (15.61) 1.100 (27.94) 0.0106 (0.269) 0.018 (0.46) 0.055 (1.39) 0.050 (1.27) 0.074 (1.88) 0.080 (2.03) 0.080 (2.03) 1.240 (31.50) 0.514 (13.06) b a pin1 h h k k l l f j1 j p c k1 t e e1 0.02 (0.51) 0.0094 (0.239) figure 12: 24-pin cdip mechanical outline: order as part no. MX803Aj

▲Up To Search▲

Price & Availability of MX803A

	To Download MX803A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .